a天堂国产 I 久久图片 I 91精品高清 I 亚洲人人玩人人添人人 I 婷婷伊人五月色噜噜精品一区 I 亚洲第一页夜 I 91日韩精品视频 I 无码人妻在线一区二区三区免费 I www.五月婷婷.com I 国产精品久久久久亚洲影视 I 91久久精品一二三 I 国产ts一区 I 91精品乱码久久蜜桃 I 成人免费观看高清 I 久久久久久国产精品免费无码 I 久久免费少妇高潮99精品 I 国产探花在线免费观看 I 亚洲精品少妇 I 亚洲综合成人亚洲 I 欧美区一区二区 I 手机福利视频 I 亚洲欧美综合另类自拍 I 久久精品视频免费播放 I 亚洲精品久久 I av免费在线免费观看 I 亚洲热综合 I 中文字幕无码专区人妻制服 I 午夜免费一区二区 I 在线亚洲精品国产一区麻豆 I 久久精品免费在线观看 I 全国最大成人网 I 亚洲欧美经典视频 I 手机av在线看 I 偷拍视频一区二区三区 I 吃奶摸下激烈视频学生软件

第一階段
Verilog Synthesis

Topic

Course overview; Introduction to synthesis, ASIC&FPGA design flows, technology libraries, wire load modeling; timing constraints, synthesis software overview

Verilog Synthesis I: Data types, numbers, continuous assignments, procedural assignments, combinational logic and flip-flop inferences

Verilog Synthesis II: Operators, if-else and case statements, intentional and unintentional latch inference

Verilog Synthesis III: Synthesis of latches and flip-flops; blocking and nonblocking assignments; synthesis of loops, tasks, functions and parameters; finite state machine design

第二階段
Implementation Technologies and System-on-Chip Concepts

Topic

Programmable logic including FPGA: History, taxonomy, architectures & device examples

“Real World ASIC Design” (Source: NEC Electronics America. Used by permission) ASIC design flow, signal integrity, design size, tests, design for manufacturing (DFM)

System-on-Chip (SoC) Concepts: SoC components, on-chip and off-chip busses, IP blocks

SoC graphics subsystems; SoC design verification

第三階段
Digital System Timing Fundamentals

Topic

Why timing matters. Scaling of wires: The dark side of Moore’s law. Combinational timing modeling and analysis by critical path method

Sequential system timing: Clocks, register timing modeling. Setup and hold path analysis

Delay-locked and phase-locked loops, module port timing characterization (pin timing)

Reset timing: Synchronous or asynchronous? Timing-driven synthesis, timing optimizations: Clock skew and register retiming, static timing analysis.

第四階段
Advanced Digital System Timing

Topic

Synchronization and metastability

Synchronizer design

Multi-clock design techniques, signaling across clock domains

Self-timed logic design