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嵌入式OS--4G手機操作系統

手機/網絡/動漫游戲開發

嵌入式OS--WinCE

單片機培訓

嵌入式硬件設計

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PowerPC嵌入式系統/編譯器優化

3G手機軟件測試、硬件測試

云計算、物聯網

開源操作系統Tiny OS開發

　

　

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曙海招聘啟示

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Overview
In this workshop, you will learn to use DFT Compiler to perform RTL and gate-level DFT checks and insert scan using top-down and bottom-up flows. The workshop will show you how to analyze the reported data to identify common DFT violations and then fix the original RTL design. The class explores essential techniques to support large, multi-million gate SOC designs including the bottom-up scan insertion flow in the logical (Design Compiler) domain. Techniques learned include: performing scan insertion in a top-down flow; meeting scan requirements for number of scan chains, maximum chain length, and reusing functional pins for scan testing; and using Adaptive Scan (DFTMAX) to insert additional DFT hardware to reduce the test time and the test data volume required for a given fault coverage. ObjectivesAt the end of this workshop the student should be able to:

• Define the test protocol for a design and customize the initialization sequence, if needed
• Perform DFT checks at both the RTL and gate levels
• State common design constructs that cause typical DFT violations
• Automatically correct certain DFT violations at the gate level using AutoFix
• Insert scan to achieve well-balanced top-level scan chains and other scan design requirements
• Write a script to perform all the steps in the DFT flow, including exporting all the required files for ATPG and place & route.
• Implement Rapid Scan Synthesis (RSS) in a top-down scan insertion flow achieving well-balanced scan chains
• Modify a bottom-up scan insertion script for full gate-level designs to use test models/ILMs with RSS and run it
• Preview top-level chain balance using test models/ILMs after block-level scan insertion and revise block-level scan architecture as needed to improve top-level scan chain balance.
• Modify a scan insertion script to include DFT-MAX Adaptive Scan compression

Audience Profile
Design and Test engineers who need to identify and fix DFT violations in their RTL or gate-level designs, insert scan into multi-million-gate SoCs, and export design files to ATPG and P&R tools Prerequisites
There are no prerequisites for this workshop. Prior experience with Design Compiler, Design Vision, and with writing Synopsys Tcl scripts is useful, but not required. Course 1.

• Introduction to Scan Testing
• DFT Compiler Flows
• DFT Compiler Setup
• Test Protocol
• DFT Design Rule Checks

2.

• DFT DRC GUI Debug
• DRC Fixing
• Top-Down Scan Insertion

3.

• Exporting Files
• High Capacity DFT Flows
• Multi-Mode DFT
• DFT MAX

Synopsys Tools Used

• DFT Compiler 2010.03-SP3
• Design Vision 2010.03-SP3
• Design Compiler 2010.03-SP3
• TetraMAX 2010.03-SP3